This invention relates to a MOS logic circuit constructed by connecting in series more than two MOSFETs, each supplied with a different logic signal between a power source and signal output terminal. More particularly, the invention relates, to a MOS logic circuit which, when one of a plurality of signal input terminals is used as an inversion circuit, assures a reduction in the variations of a circuit property depending on the position of said signal input terminal.
FIG. 1A shows the circuit arrangement of the conventional 2-input CMOS NAND gate. In this circuit arrangement, two current passages consisting of P channel MOSFETs 2, 3 are connected in parallel between a positive power source V.sub.DD and logic signal output terminal 1; and two current passages consisting of N channel MOSFETs 4, 5 are connected in series between said logic signal output terminal 1 and ground voltage source V.sub.SS. The gate electrode of said MOSFET 2 and that of said MOSFET 4 are jointly connected to a logic signal input terminal 6 which is supplied with a logic input signal IN1. The gate electrode of said MOSFET 3 and that of said MOSFET 5 are jointly connected to a logic signal input terminal 7 which is supplied with a logic input signal IN2.
With the above-mentioned 2-input type NAND gate, a logic output signal OUT whose level is determined by a combination of the logic levels of said logic input signals IN1, IN2 is sent forth from the logic signal output terminal 1. The 2-input type NAND gate is indicated by a symbol in FIG. 1B. The conventional 2-input NAND gate of FIG. 1A is sometimes applied as an inverter in which two independent input signals IN1, IN2 are supplied to the corresponding input terminals 6, 7; a voltage having the level V.sub.DD (high level) is always impressed as one of the input signals; and a signal having a high or low level is supplied, thereby inverting one input signal. However, the conventional 2-input NAND gate of FIG. 1A has the drawback that when said NAND gate is used as an inverter by operating one of the input terminals, circuit properties such as a switching speed and circuit threshold voltage are governed by the position of the input terminal and undergo changes. The application of one of the input terminals as an inverter results in changes in the switching speed or circuit threshold voltage, depending on the position of said input terminal. This event occurs not only in the 2 -input NAND gate but also in a NAND gate or NOR gate having more than two input terminals.